A sample/hold circuit is mainly utilized in the front stage of ADC (analog to digital converter) to increase data accuracy while sampling data. The sample-and-hold circuit is thus a critical factor on the whole circuit performance. It is widely applied in the electronic device. For instance, as the CD/DVD chip operated at burning mode, it is demanded that a sample-and-hold (S/H) circuit ensures the output voltage stable while sampling or holding data. Generally, the sample-and-hold circuit may have many forms to present. Following switched operation amplifier (SOP) is the common one.
Referring to FIG. 1, a SOP circuit according to prior art is shown. An operation amplifier (OP) having a positive terminal and a negative terminal is connected to a switch S/H. The switch S/H is coupled to a buffer and a capacitor Ch which is connected to ground. The buffer has an output voltage VOUT feedback to the negative terminal to form a voltage VN. As the switch S/H is on, it is a sampling mode having the voltage VOUT feedback into the negative terminal of the OP to make the voltage VOUT equal to an input voltage VP received from the positive terminal. In the meantime, the capacitor Ch is charged to follow the input voltage VP. As the switch S/H is off, it is the holding mode that the output voltage VOUT is provided only from the capacitor Ch so that the voltage VOUT is approximately equivalent to the input voltage VP.
FIG. 2 shows detailed circuit diagram of the SOP according to FIG. 1. The SOP includes an amplifier circuit 10, a biased circuit 12 and a buffer circuit 14. The amplifier circuit 10 composed of transistors M0 to M12 has a differential pair (M1, M2) to receive the input voltage VP and the voltage VN which is feedback from the output voltage VOUT respectively. The biased circuit 12 composed of transistors M15 to M24 generates biased voltages bp0, bpc, bnc, bn0 for the amplifier circuit 10 and the buffer circuit 14, which is composed of transistors M13, M14 and the capacitor Ch. The buffer circuit 14 generates the output voltage VOUT according to the voltage VNZ at the node NZ. The output voltage VOUT is feedback to the negative terminal of the differential pair (M1, M2) to form the voltage VN.
In the sampling mode (switch S switched on, switch H switched off), the transistors M7, M8, M9, M10 are in active region by either biased voltage bpc or bnc, and the capacitor Ch is charged to a predetermined voltage (VP) via the node NZ so that the output voltage VOUT equals to the predetermined voltage (VP). Worthwhile to note, the biased voltages bnc, bn0 are generated by two current sources i1, i2 through the transistors M15, M17, which are diode-connected transistor. The biased voltages bnc, bn0 then derives mirror currents through current mirror (transistors M18, M20, M19, M21), while biased voltages bpc, bp0 is arisen through PMOS transistors M22, M23, M24. Still, the biased voltage bn0 is fed into a gate of transistor M0 of the amplifier circuit 10 to generate a tail current it. The tail current it then branched into two current it1, and it2 on transistors M1, M2 of the differential pair, where it1=(½)it+Δi, and it2=(½)it−Δi.
Furthermore, the current it1 generates a mirror current it3 through current mirror (M3, M5). The current it3 flows through transistors M7, M9, M11 and next again generates mirror current it4 through transistor M12 by the current mirror relationship. A mirror current it5 of the current it2 flows through transistors M4, M6, M8. The mirror current it5 associated with the mirror current it4 determines the voltage VNZ of the node NZ by charging the capacitor Ch. The voltage VNZ turns on the transistor M13 such that the output voltage VOUT equals to the voltage VN, and equals to the input voltage VP.
In the holding mode (switch H switched on, switch S switched off), the transistors M7, M8, M9, M10 are in cut-off region due to the gates of the transistors M7 and M8 are connected to VDD (for PMOS) and the gates of the transistors M9 and M10 are connected to ground (for NMOS). The input voltage VP can not affect the output voltage VOUT. The output voltage VOUT is kept to a value determined by the capacitor Ch.
However, many problems are found in accordance with aforementioned prior art. For instance, ground voltage drifted due to turning on the transistors M7, M8, M9, M10 in the sampling mode, will generate about 400 mA, which depends on the size of the transistors, such as channel width/channel length (W/L). In the holding mode, all of the transistors M7, M8, M9, M10 are turned off, which results in current variation due to effect of stray resistors while upon switching. The current variation will affect the ground potential variation, further, affecting the output voltage, or even causing malfunctions.
In addition, two sets of current source i1, i2 in the biased circuit 12 are utilized to generate biased voltages bn0, bnc, bp0, bpc according to prior art. Thus, if it is desired to shift the bandwidth of the SOP, a direct method is to change the current of the current sources i1 and i2. However, owing to cascade structure of the transistors (M15 to M21 are coupled among another), any biased current change will shift the biased voltage, which results in the transistors cannot work at optimum working range. Consequently, bandwidth variability is restricted seriously.
Another disadvantage is the setting limitation. The biased voltages of the transistors M7, M8, M9, M10 are switched rapidly between the biased voltage bnc to ground or the biased voltage bpc to VDD. Therefore, the voltages on gates of M7, M8, M9 and M10 will be set individually in the sampling mode. If the setting speed of the biased voltage bnc to ground is different from the setting speed of the biased voltage bpc to VDD, it will result in the output voltage temporarily unstable, and the setting time is extended.
An object of the present invention is to propose a newly structure of SOP to solve above problems.